Abstract

In the present study, a high-speed, 8-bit digital-to-analog converter with a sampling rate of about 2.8 billion samples per second was designed and simulated. In this regard, first, the well-known digital-to-analog converters such as resistive voltage divider, capacitive voltage divider, digital-to-analog converters based on current conduction, binary converter, and thermometer were introduced. Then, to achieve the desired speed, various separated R-2R binary-thermometer and resistive ladder structures were evaluated and the best structures were selected and implemented. The production line, dual-channel, and other well-known structures were introduced and their advantages and disadvantages were discussed. Mismatch of resistors and current sources, which play an essential role in resistive ladder structure, were carefully analyzed. Simulations were performed using the CMOS model of TSMC company in 0.35 μ process via the HSPICE software. The effects of mismatches in the corners and temperature were considered in all simulations. The simulation results, after Layout, implied acceptable performance of the 8-bit digital-to-analog converter with a speed of 2.8, signal-to-noise ratio of 49.4 dB, SFDR of about 63 dB, maximum power consumption of 218 mW, and 3. 3 V power supply. The effective area of the designed chip was about 0.54 mm2. Specifications of the designed digital-to-analog converter were discussed in comparison with the previous studies and the significant differences were present.